A. Field of the Invention
The present invention relates to a high-power vertical insulated gate semiconductor device, and in more detail, to a trench gate superjunction semiconductor device having a trench gate, which has a trench, an insulator film formed therein and a control electrode filling the trench with the insulator film held between, and having a superjunction layer in a semiconductor substrate.
B. Description of the Related Art
In recent years, in compliance with requirements for downsizing and performance enhancement in power source equipment in the field of power electronics, efforts have been concentrated on a power semiconductor device to improve the performance in obtaining a high breakdown voltage, a high current capacity and along with this, a low power loss, a high breakdown capability and a high operation speed. A superjunction substrate is known as a substrate structure of a power semiconductor device for enabling a device to obtain such a high breakdown voltage, a high current capacity and a low power loss. Moreover, for a surface structure of a power semiconductor device, a vertical or trench MOS power device has been proposed.
For a substrate structure of a power semiconductor device, two kinds of substrates, a semiconductor substrate having a single conductivity type and a superjunction substrate, are widely known. Here, a superjunction substrate is a substrate including a superjunction layer, a layer in which a plurality of first conductivity type semiconductor regions (for example, n-type drift regions) and a plurality of second conductivity type semiconductor regions (for example, p-type partition regions) are alternately joined.
The superjunction substrate, by forming the superjunction layer, can expand the space charge region of the whole superjunction layer at turning-off even when an impurity concentration in each layer of the superjunction layer is high. Therefore, the superjunction substrate is considered to be more advantageous than a semiconductor substrate having a single conductivity type in that the superjunction substrate can reduce on-resistance particularly in a high breakdown voltage semiconductor device.
As a technology for a power device using a superjunction semiconductor substrate, the following technology is known (see JP-A-2004-119611, for example). In the technology, in a power MOSFET having a superjunction structure, an impurity concentration in a p RESURF layer is made to have a distribution of being reduced in the direction of the depth (an inclined profile). This causes a reduction in a breakdown voltage, which is due to an unbalanced amount between the amount of impurity in the p RESURF layer and the amount of impurity in an n drift layer, smaller than that in a previous device.
Furthermore, a semiconductor device is known which has a high breakdown voltage together with reduced on-resistance by improving a structure of a drift region in which a depletion layer is produced in a turned-off state (see JP-A-09-266311, for example).
Next, explanations will be made about the surface structures of power semiconductor devices. As surface structures of power semiconductor devices, two kinds of structures are known. One is a planar structure in which a MOS gate is provided on a flat plate. The other is a trench structure in which a MOS gate is formed by filling a trench. A trench MOS power device has a trench gate structure in which a number of trench MOS cells, each having a trench side wall provided as a channel region, are arranged in a line on a semiconductor substrate. In general, a trench MOS device is considered to be more advantageous than a planar MOS device in that its performance is easily improved by reducing resistance of the channel.
In a recent vertical device, a trench type device having a structure with gate electrodes filling trenches has become a focus of attention since the structure allows low on-resistance characteristics to be easily obtained. For such a vertical trench type MOS power device, a vertical MOSFET device is known together with its manufacturing method. In the device, the input capacitance is reduced without increasing a threshold voltage of a switching operation, by which the driving loss and switching loss are significantly improved (see JP-A-05-335582, for example).
Moreover, a technology is known by which a MOSFET having the gates formed inside the trenches are miniaturized to simplify the manufacturing process (see JP-A-04-233765, for example).
Furthermore, an insulated gate bipolar semiconductor device is known together with a method for its manufacture. The device has a low on-voltage though the device has a high operation speed and a high breakdown voltage (see JP-A-04-146674, for example).
An example of structures of vertical MOSFETs, disclosed in the patent documents JP-A-2004-119611, JP-A-09-266311, JP-A-05-335582, JP-A-04-233765 and JP-A-04-146674, is shown in FIG. 23. Moreover, an example of structures of vertical IGBTs, disclosed in the above patent documents, is shown in FIG. 24. Here, related art will be shown with reference to FIG. 23. Furthermore, in FIG. 24, similar components to those in FIG. 23 are denoted by the same reference numerals. In FIG. 23, a semiconductor substrate is formed of n+-type drain layer 101 and n−-type drain layer 102. On the surface of n−-type drain layer 102, p-type channel region 103 is provided.
A plurality of trenches 104 are formed from the surface of p−-type channel region 103 to a depth reaching n−-type drain layer 102. On the surface of each trench 104, gate oxide film 105 is formed. Further, the inside of each trench 104 is filled with gate electrode 106 of, for example, polycrystalline silicon. On the surface of p−-type channel region 103, p+-type body region 107 is formed approximately at the midpoint between trenches 104 that are adjacent to each other. Between p+-type body region 107 and trench 104, n++-type source region 108 is formed.
Moreover, on gate electrode 106, insulator film 109 is formed, on which metal electrode 110 of metal such as aluminum, for example, is further formed over the whole surface of a cell region. Insulator film 109 isolates gate electrode 106 from metal electrode 110. Metal electrode 110 is formed so as to be in ohmic contact with n++-type source region 108 and p+-type body region 107. Also on the surface of the semiconductor substrate opposite to the surface on which metal electrode 110 is formed, metal electrode 111 is formed.
In the vertical MOSFET or the vertical IGBT, by applying a voltage equal to the specified threshold value or more to gate electrode 106, an n-type inversion layer is formed along each trench 104 in p-type channel region 103 to provide a current path between each n++-type source region 108 and each of drain layers 101 and 102 in the n-type semiconductor substrate. With the current path thus provided, the region between the source and the drain of the vertical MOSFET is brought into a turned-on state. By reducing the voltage applied to gate electrode 106 to the threshold value or less, the n-type inversion layer in p-type channel region 103 disappears. Thus, the region between the source and the drain of the vertical MOSFET is brought into a turned-off state.
In the vertical MOSFET with the above arrangement, a vertical current path is formed along each trench 104. Therefore, the area of a current path is significantly enlarged compared with that in a planar vertical MOSFET. This provides the advantage of allowing on-resistance to be reduced, whereas in the trench vertical MOSFET, the electric field strength at the bottom of trench 104 is increased to reduce the breakdown voltage of the semiconductor device. Furthermore, in the state in which the electric field strength at the bottom of trench 104 is high (when the semiconductor substrate is turned-off), carriers are injected into gate oxide film 105 to degrade the long term reliability of the MOS gate section.
Next to this, electric field strength distributions will be shown about the trench gate MOSFET with the structure shown in FIG. 23 and a diode structure without trench being formed, both at avalanche breakdown. FIG. 25 is a graph showing the respective electric field strength distributions of the trench gate MOSFET and the diode structure without trench being formed, both at avalanche breakdown. In FIG. 25, the vertical axis represents an electric field strength (V/cm) and the horizontal axis represents a distance (μm) in the direction of the depth of the trench from the surface of p-type channel region 103. Distribution 121 represents the electric field strength distribution in the case without trench and distribution 122 represents the electric field strength distribution in the case with trench (trench gate MOSFET).
In FIG. 23, trench 104 is shown to have a rectangular cross sectional shape. Actually, however, the bottom of trench 104 is formed into a half-cylinder-like shape having a radius of curvature of 0.6 μm and extending in a direction approximately perpendicular to the direction in which rows of trenches 104 are formed to be aligned side by side. Gate oxide film 105 is formed along the inner surface of trench 104 with a thickness of 0.1 μm. The inside of gate oxide film 105 is filled with gate electrode 106 with a radius of curvature at the bottom being 0.5 μm. Further, the spacing between trenches 104 is 5 μm. The impurity concentration in the n-layer is determined to be 2.5×1014 cm−3.
In FIG. 25, it is shown that the electric field strength of the trench gate MOSFET indicated with distribution 122 increases abruptly at the bottom of trench 104 compared with the case of forming no trench 104 indicated with distribution 121. The trench gate MOSFET causes avalanche breakdown at this section only to provide a lower breakdown voltage than that in the case without trench 104.
As a measure for reducing the increase in the electric field strength at the bottom of the trench of the vertical MOSFET disclosed in each of the patent documents JP-A-2004-119611, JP-A-09-266311, JP-A-05-335582, JP-A-04-233765 and JP-A-04-146674, and for enhancing the breakdown voltage, a structure of a semiconductor device and a method for its manufacture is known. In the structure and the method, a p-type layer is formed at the bottom of a trench or a p-type channel layer is deeply formed (see, Hidefumi Takaya et al., “Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)—A 60 V Ultra Low On-Resistance Novel MOSFET with Superior Internal Body Diode—”, Proceedings of ISPSD 2005, pp. 43-46 (2005), and T. Dyer et al., “Monolithic Integration of Trench Vertical DMOS (VDMOS) Power Transistors into BCD Process”, Proceedings of ISPSD 2005, pp. 47-50 (2005), for example).
By the related art described in Takaya's or Dyer's document, the breakdown voltage of a semiconductor device can be enhanced by reducing the electric field strength at the bottom of the trench. The enhanced breakdown voltage, however, caused an accompanying problem of abruptly raising the on-voltage of the semiconductor device, and the measure for lowering the on-voltage caused a problem of abruptly reducing the breakdown voltage of the semiconductor device.
In order to solve the problems with the foregoing related art, an object of the invention is to provide a semiconductor device that can enhance a breakdown voltage as a characteristic at turning-off by weakening the electric field strength at the bottom of a trench, and at the same time, can lower the on-voltage as a characteristic in a turned-on state and a method of manufacturing the semiconductor device.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.